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The ISCAS85 Benchmarks in FHDL Format
The three files that constitute this tech report are ISCAS85.fhdl.zip, ISCAS85.InputVectors.zip, and ISCAS85.VectorGenerators.zip. The first file contains the 10 ISCAS85 benchmarks in FHDL format, plus the smoke-test circuit ...
The Inversion-Algorithm Software
The software in this package implements four versions of the Inversion algorithm. Four executable files are produced.These executables are used in much the same way as the FHDL package, but only AND, OR, NAND, NOR, NOT, ...
The Shadow Algorithm Software Package
This is the software described in the technical report “The Shadow Algorithm: …” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
The Hyper-Linear Package
The Hyper-Linear package is the core of the hyper-linear simulation technique described in Reference 1. Given the specification of a Boolean function, the package will detect all partial and total symmetries and return the ...
The FHDL Rom Tools
The FHDL (Functional Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying ...
The Inversion Algorithm for Digital Simulation
The Inversion Algorithm is an event-driven algorithm, whose performance rivals or exceeds that of Levelized Compiled code simulation, even at activity rates of 50% or more. The Inversion Algorithm has several unique ...
The FHDL Manual
The Functional Hardware Design Language can be used to create all parts of a digital design. It can be used to design logic-level circuits with ordinary gates, flip-flops and mid-sized functional blocks. It is hierarchical ...
The Functional Hardware Design Language
The Functional Hardware Design Language is an expandable language that is designed to make it easy to specify gate-level. FHDL currently supports the specification of gates, high-level functional blocks, state machines, ...
Using the Connlib Package to Obtain Parsed Netlist Data
The connlib package can be used to obtain parsed netlist data from “.ckt” files. These files must be created using the Functional Hardware Description Language FHDL. This data can be used in any way you choose. The ISCAS85 ...
Unit Delay Scheduling for the Inversion Algorithm
The Inversion Algorithm is an event driven algorithm whose performance meets or exceeds that of Levelized Compiled Code simulation, even when the activity rate is unrealistically high. Existing implementations of the ...