Now showing items 1-18 of 18

  • Event Driven Simulation without Loops or Conditionals 

    Maurer, Peter M. (2009-11-05)
    Event driven simulation normally requires a great deal of computation to perform a multitude of different tasks. The purpose of this paper is to show that none of these computations are necessary. Most computations are ...
  • The FHDL LCC Simulator 

    Maurer, Peter M. (2009-11-13)
    This software is the levelized compiled code simulator for the FHDL system. Given a .ckt file, it will compile the file into a C program that simulates the circuit. The C program will be compiled into an executable by the ...
  • The FHDL Manual 

    Maurer, Peter M. (2009-10-28)
    The Functional Hardware Design Language can be used to create all parts of a digital design. It can be used to design logic-level circuits with ordinary gates, flip-flops and mid-sized functional blocks. It is hierarchical ...
  • The FHDL Rom Tools 

    Maurer, Peter M. (2009-11-13)
    The FHDL (Functional Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying ...
  • The Functional Hardware Design Language 

    Maurer, Peter M. (2009-10-28)
    The Functional Hardware Design Language is an expandable language that is designed to make it easy to specify gate-level. FHDL currently supports the specification of gates, high-level functional blocks, state machines, ...
  • The Hyper-Linear Package 

    Maurer, Peter M. (2009-11-13)
    The Hyper-Linear package is the core of the hyper-linear simulation technique described in Reference 1. Given the specification of a Boolean function, the package will detect all partial and total symmetries and return the ...
  • HyperSim 

    Maurer, Peter M. (2009-11-13)
    This software package implements the simulation algorithm described in the tech report “Using GF(2) matrices in Simulation and Logic Synthesis” found in this archive. (http://hdl.handle.net/2104/5263). This package is part ...
  • The Inversion Algorithm for Digital Simulation 

    Maurer, Peter M. (2009-11-05)
    The Inversion Algorithm is an event-driven algorithm, whose performance rivals or exceeds that of Levelized Compiled code simulation, even at activity rates of 50% or more. The Inversion Algorithm has several unique ...
  • The Inversion-Algorithm Software 

    Maurer, Peter M. (2009-11-13)
    The software in this package implements four versions of the Inversion algorithm. Four executable files are produced.These executables are used in much the same way as the FHDL package, but only AND, OR, NAND, NOR, NOT, ...
  • The ISCAS85 Benchmarks in FHDL Format 

    Maurer, Peter M. (2009-11-13)
    The three files that constitute this tech report are ISCAS85.fhdl.zip, ISCAS85.InputVectors.zip, and ISCAS85.VectorGenerators.zip. The first file contains the 10 ISCAS85 benchmarks in FHDL format, plus the smoke-test circuit ...
  • The ISCAS89 Benchmarks in FHDL Format 

    Maurer, Peter M. (2009-11-13)
    The .zip file contains each of the ISCAS89 Benchmarks in FHDL format. Also included is a random vector generator file for each circuit. (For what it’s worth.) The generators are written in the DGL language.
  • The Parallel Technique Software Package 

    Maurer, Peter M. (2009-11-13)
    This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
  • The PC-Set Method Software Package 

    Maurer, Peter M. (2009-11-13)
    This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
  • The Shadow Algorithm Software Package 

    Maurer, Peter M. (2009-11-13)
    This is the software described in the technical report “The Shadow Algorithm: …” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
  • Three-Valued Simulation with the Inversion Algorithm 

    Maurer, Peter M. (2009-11-05)
    The Inversion Algorithm is an event-driven logic simulation technique that is competitive with Levelized Compiled Code Simulation. Previous versions of the Inversion Algorithm have been limited to purely binary simulation. ...
  • Two New Techniques for Unit-Delay Compiled Simulation 

    Maurer, Peter M. (2009-11-05)
    The PC-set method and the parallel technique are two methods for generating compiled unit-delay simulations of acyclic circuits. The PC-set method analyzes the network, determines the set of potential change times for each ...
  • Unit Delay Scheduling for the Inversion Algorithm 

    Maurer, Peter M. (2009-11-05)
    The Inversion Algorithm is an event driven algorithm whose performance meets or exceeds that of Levelized Compiled Code simulation, even when the activity rate is unrealistically high. Existing implementations of the ...
  • Using the Connlib Package to Obtain Parsed Netlist Data 

    Maurer, Peter M. (2009-11-05)
    The connlib package can be used to obtain parsed netlist data from “.ckt” files. These files must be created using the Functional Hardware Description Language FHDL. This data can be used in any way you choose. The ISCAS85 ...