• Login
    Search 
    •   BEARdocs Home
    • School of Engineering & Computer Science
    • Search
    •   BEARdocs Home
    • School of Engineering & Computer Science
    • Search
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Search

    Show Advanced FiltersHide Advanced Filters

    Filters

    Use filters to refine the search results.

    Now showing items 1-10 of 18

    • Sort Options:
    • Relevance
    • Title Asc
    • Title Desc
    • Issue Date Asc
    • Issue Date Desc
    • Results Per Page:
    • 5
    • 10
    • 20
    • 40
    • 60
    • 80
    • 100
    Thumbnail

    The Inversion Algorithm for Digital Simulation 

    Maurer, Peter M. (2009-11-05)
    The Inversion Algorithm is an event-driven algorithm, whose performance rivals or exceeds that of Levelized Compiled code simulation, even at activity rates of 50% or more. The Inversion Algorithm has several unique ...
    Thumbnail

    Three-Valued Simulation with the Inversion Algorithm 

    Maurer, Peter M. (2009-11-05)
    The Inversion Algorithm is an event-driven logic simulation technique that is competitive with Levelized Compiled Code Simulation. Previous versions of the Inversion Algorithm have been limited to purely binary simulation. ...
    Thumbnail

    The PC-Set Method Software Package 

    Maurer, Peter M. (2009-11-13)
    This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
    Thumbnail

    The FHDL Manual 

    Maurer, Peter M. (2009-10-28)
    The Functional Hardware Design Language can be used to create all parts of a digital design. It can be used to design logic-level circuits with ordinary gates, flip-flops and mid-sized functional blocks. It is hierarchical ...
    Thumbnail

    Two New Techniques for Unit-Delay Compiled Simulation 

    Maurer, Peter M. (2009-11-05)
    The PC-set method and the parallel technique are two methods for generating compiled unit-delay simulations of acyclic circuits. The PC-set method analyzes the network, determines the set of potential change times for each ...
    Thumbnail

    The Functional Hardware Design Language 

    Maurer, Peter M. (2009-10-28)
    The Functional Hardware Design Language is an expandable language that is designed to make it easy to specify gate-level. FHDL currently supports the specification of gates, high-level functional blocks, state machines, ...
    Thumbnail

    Event Driven Simulation without Loops or Conditionals 

    Maurer, Peter M. (2009-11-05)
    Event driven simulation normally requires a great deal of computation to perform a multitude of different tasks. The purpose of this paper is to show that none of these computations are necessary. Most computations are ...
    Thumbnail

    The Shadow Algorithm Software Package 

    Maurer, Peter M. (2009-11-13)
    This is the software described in the technical report “The Shadow Algorithm: …” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
    Thumbnail

    The Hyper-Linear Package 

    Maurer, Peter M. (2009-11-13)
    The Hyper-Linear package is the core of the hyper-linear simulation technique described in Reference 1. Given the specification of a Boolean function, the package will detect all partial and total symmetries and return the ...
    Thumbnail

    The FHDL Rom Tools 

    Maurer, Peter M. (2009-11-13)
    The FHDL (Functional Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying ...
    • 1
    • 2

    Copyright © Baylor® University All rights reserved. Legal Disclosures.
    Baylor University Waco, Texas 76798 1-800-BAYLOR-U
    Baylor University Libraries | One Bear Place #97148 | Waco, TX 76798-7148 | 254.710.2112 | Contact: libraryquestions@baylor.edu
    If you find any errors in content, please contact librarywebmaster@baylor.edu
    DSpace software copyright © 2002-2016  DuraSpace
    Contact Us | Send Feedback
    TDL
    Theme by 
    Atmire NV
     

     

    Browse

    All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CommunityBy Issue DateAuthorsTitlesSubjects

    My Account

    Login

    Discover

    AuthorMaurer, Peter M. (18)Subject
    Digital Simulation (18)
    Event Driven Simulation (4)Hardware Design Language (3)Benchmarks (2)Compiled Simulation (2)Conjugate Symmetry (2)Inversion Algorithm (2)Combinational Benchmarks (1)Differential Simulation (1)Event-Driven Simulation (1)... View MoreDate Issued2009 (18)Has File(s)Yes (18)

    Copyright © Baylor® University All rights reserved. Legal Disclosures.
    Baylor University Waco, Texas 76798 1-800-BAYLOR-U
    Baylor University Libraries | One Bear Place #97148 | Waco, TX 76798-7148 | 254.710.2112 | Contact: libraryquestions@baylor.edu
    If you find any errors in content, please contact librarywebmaster@baylor.edu
    DSpace software copyright © 2002-2016  DuraSpace
    Contact Us | Send Feedback
    TDL
    Theme by 
    Atmire NV