The connlib package can be used to obtain parsed netlist data from “.ckt” files. These files must be created using the Functional Hardware Description Language FHDL. This data can be used in any way you choose. The ISCAS85 ...

This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.

This software is the levelized compiled code simulator for the FHDL system. Given a .ckt file, it will compile the file into a C program that simulates the circuit. The C program will be compiled into an executable by the ...

The Hyper-Linear package is the core of the hyper-linear simulation technique described in Reference 1. Given the specification of a Boolean function, the package will detect all partial and total symmetries and return the ...

The FHDL (Functional Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying ...

Event driven simulation normally requires a great deal of computation to perform a multitude of different tasks. The purpose of this paper is to show that none of these computations are necessary. Most computations are ...

The PC-set method and the parallel technique are two methods for generating compiled unit-delay simulations of acyclic circuits. The PC-set method analyzes the network, determines the set of potential change times for each ...

This is the software described in the technical report “The Shadow Algorithm: …” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.

This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.

The Functional Hardware Design Language is an expandable language that is designed to make it easy to specify gate-level. FHDL currently supports the specification of gates, high-level functional blocks, state machines, ...