Now showing items 1-10 of 18
The Inversion Algorithm for Digital Simulation
The Inversion Algorithm is an event-driven algorithm, whose performance rivals or exceeds that of Levelized Compiled code simulation, even at activity rates of 50% or more. The Inversion Algorithm has several unique ...
Three-Valued Simulation with the Inversion Algorithm
The Inversion Algorithm is an event-driven logic simulation technique that is competitive with Levelized Compiled Code Simulation. Previous versions of the Inversion Algorithm have been limited to purely binary simulation. ...
The PC-Set Method Software Package
This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
The FHDL Manual
The Functional Hardware Design Language can be used to create all parts of a digital design. It can be used to design logic-level circuits with ordinary gates, flip-flops and mid-sized functional blocks. It is hierarchical ...
Two New Techniques for Unit-Delay Compiled Simulation
The PC-set method and the parallel technique are two methods for generating compiled unit-delay simulations of acyclic circuits. The PC-set method analyzes the network, determines the set of potential change times for each ...
The Functional Hardware Design Language
The Functional Hardware Design Language is an expandable language that is designed to make it easy to specify gate-level. FHDL currently supports the specification of gates, high-level functional blocks, state machines, ...
Event Driven Simulation without Loops or Conditionals
Event driven simulation normally requires a great deal of computation to perform a multitude of different tasks. The purpose of this paper is to show that none of these computations are necessary. Most computations are ...
The Shadow Algorithm Software Package
This is the software described in the technical report “The Shadow Algorithm: …” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
The Hyper-Linear Package
The Hyper-Linear package is the core of the hyper-linear simulation technique described in Reference 1. Given the specification of a Boolean function, the package will detect all partial and total symmetries and return the ...
The FHDL Rom Tools
The FHDL (Functional Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying ...