Now showing items 1-10 of 18
The Hyper-Linear Package
The Hyper-Linear package is the core of the hyper-linear simulation technique described in Reference 1. Given the specification of a Boolean function, the package will detect all partial and total symmetries and return the ...
The FHDL Rom Tools
The FHDL (Functional Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying ...
Event Driven Simulation without Loops or Conditionals
Event driven simulation normally requires a great deal of computation to perform a multitude of different tasks. The purpose of this paper is to show that none of these computations are necessary. Most computations are ...
Two New Techniques for Unit-Delay Compiled Simulation
The PC-set method and the parallel technique are two methods for generating compiled unit-delay simulations of acyclic circuits. The PC-set method analyzes the network, determines the set of potential change times for each ...
The Shadow Algorithm Software Package
This is the software described in the technical report “The Shadow Algorithm: …” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
The Parallel Technique Software Package
This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.
The Functional Hardware Design Language
The Functional Hardware Design Language is an expandable language that is designed to make it easy to specify gate-level. FHDL currently supports the specification of gates, high-level functional blocks, state machines, ...
The ISCAS85 Benchmarks in FHDL Format
The three files that constitute this tech report are ISCAS85.fhdl.zip, ISCAS85.InputVectors.zip, and ISCAS85.VectorGenerators.zip. The first file contains the 10 ISCAS85 benchmarks in FHDL format, plus the smoke-test circuit ...
The ISCAS89 Benchmarks in FHDL Format
The .zip file contains each of the ISCAS89 Benchmarks in FHDL format. Also included is a random vector generator file for each circuit. (For what it’s worth.) The generators are written in the DGL language.
The Inversion-Algorithm Software
The software in this package implements four versions of the Inversion algorithm. Four executable files are produced.These executables are used in much the same way as the FHDL package, but only AND, OR, NAND, NOR, NOT, ...