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    The Hyper-Linear Package 

    Maurer, Peter M. (2009-11-13)
    The Hyper-Linear package is the core of the hyper-linear simulation technique described in Reference 1. Given the specification of a Boolean function, the package will detect all partial and total symmetries and return the ...
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    The FHDL Rom Tools 

    Maurer, Peter M. (2009-11-13)
    The FHDL (Functional Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying ...
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    The Inversion Algorithm for Digital Simulation 

    Maurer, Peter M. (2009-11-05)
    The Inversion Algorithm is an event-driven algorithm, whose performance rivals or exceeds that of Levelized Compiled code simulation, even at activity rates of 50% or more. The Inversion Algorithm has several unique ...
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    Using the Connlib Package to Obtain Parsed Netlist Data 

    Maurer, Peter M. (2009-11-05)
    The connlib package can be used to obtain parsed netlist data from “.ckt” files. These files must be created using the Functional Hardware Description Language FHDL. This data can be used in any way you choose. The ISCAS85 ...
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    The ISCAS89 Benchmarks in FHDL Format 

    Maurer, Peter M. (2009-11-13)
    The .zip file contains each of the ISCAS89 Benchmarks in FHDL format. Also included is a random vector generator file for each circuit. (For what it’s worth.) The generators are written in the DGL language.
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    The Inversion-Algorithm Software 

    Maurer, Peter M. (2009-11-13)
    The software in this package implements four versions of the Inversion algorithm. Four executable files are produced.These executables are used in much the same way as the FHDL package, but only AND, OR, NAND, NOR, NOT, ...
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    HyperSim 

    Maurer, Peter M. (2009-11-13)
    This software package implements the simulation algorithm described in the tech report “Using GF(2) matrices in Simulation and Logic Synthesis” found in this archive. (http://hdl.handle.net/2104/5263). This package is part ...
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    The FHDL LCC Simulator 

    Maurer, Peter M. (2009-11-13)
    This software is the levelized compiled code simulator for the FHDL system. Given a .ckt file, it will compile the file into a C program that simulates the circuit. The C program will be compiled into an executable by the ...
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    AuthorMaurer, Peter M. (18)Subject
    Digital Simulation (18)
    Event Driven Simulation (4)Hardware Design Language (3)Benchmarks (2)Compiled Simulation (2)Conjugate Symmetry (2)Inversion Algorithm (2)Combinational Benchmarks (1)Differential Simulation (1)Event-Driven Simulation (1)... View MoreDate Issued2009 (18)Has File(s)Yes (18)

    Copyright © Baylor® University All rights reserved. Legal Disclosures.
    Baylor University Waco, Texas 76798 1-800-BAYLOR-U
    Baylor University Libraries | One Bear Place #97148 | Waco, TX 76798-7148 | 254.710.2112 | Contact: libraryquestions@baylor.edu
    If you find any errors in content, please contact librarywebmaster@baylor.edu
    DSpace software copyright © 2002-2016  DuraSpace
    Contact Us | Send Feedback
    TDL
    Theme by 
    Atmire NV