The FHDL Manual
| dc.contributor.author | Maurer, Peter M. | |
| dc.date.accessioned | 2009-10-28T15:46:02Z | |
| dc.date.available | 2009-10-28T15:46:02Z | |
| dc.date.issued | 2009-10-28T15:46:02Z | |
| dc.description.abstract | The Functional Hardware Design Language can be used to create all parts of a digital design. It can be used to design logic-level circuits with ordinary gates, flip-flops and mid-sized functional blocks. It is hierarchical in nature and can support any type of hierarchical design. It can be used to design ROMs, PLAs, and Algorithmic State Machines. Simulations can be controlled through a high-level-language interface. This interface can be used to design test benches and to perform component-level testing on hierarchical designs. A powerful macro language can be used to create parameterized functional blocks and expression-level circuits. The language is extensible and may provide other features in the future. | en |
| dc.format.extent | 300515 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/2104/5445 | |
| dc.language.iso | en_US | |
| dc.license | GPL | en |
| dc.subject | Hardware Design Language | en |
| dc.subject | Digital Simulation | en |
| dc.title | The FHDL Manual | en |