Developing industrial strength UVM for academic resesarch and teaching.
| dc.contributor.advisor | Schubert, Keith Evan. | |
| dc.creator | Onwubuya, George M., 1991- | |
| dc.creator.orcid | 0000-0002-1648-2804 | |
| dc.date.accessioned | 2020-11-05T15:06:33Z | |
| dc.date.available | 2020-11-05T15:06:33Z | |
| dc.date.created | 2020-08 | |
| dc.date.issued | 2020-07-30 | |
| dc.date.submitted | August 2020 | |
| dc.date.updated | 2020-11-05T15:06:34Z | |
| dc.description.abstract | The Universal Verification Methodology (UVM) has been getting attention from researchers and the functional verification community for a little over decade. Its flexibility, reusability and reliability features are suitable for the design verification of multifaceted chip systems thus making it attractive for the verification industry. Similarly researchers frequently explore and utilize UVM to enhance its verification capabilities of system-on-chip (SoC) and application specific integrated circuits (ASIC). For a long time UVM learning and training has been tailored to suit the needs of seasoned verification engineers. Recent books have sought to address the needs of novice verification engineers, however UVM testbenches lack the standard required by the verification industry. This thesis outlines steps required in building a typical UVM testbench while also highlighting the important industry standards that must be maintained. In the first lab a UVM testbench is built to verify a trivial design. UVM components are constructed using a step-by-step guide with a detailed description of the UVM code. In the second lab a simple APB finite state machine is verified. This lab includes a verification plan, assertion coverage and functional coverage. These features are widely used by the verification industry to create a more robust verification environment. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | https://hdl.handle.net/2104/11137 | |
| dc.language.iso | en | |
| dc.rights.accessrights | Worldwide access | |
| dc.subject | Universal Verification Methodology. SystemVerilog. Testbench. Verification. | |
| dc.title | Developing industrial strength UVM for academic resesarch and teaching. | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.department | Baylor University. Dept. of Electrical & Computer Engineering. | |
| thesis.degree.grantor | Baylor University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | M.S.E.C.E. |
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