Computer Science Technical Reports
Permanent URI for this collectionhttps://hdl.handle.net/2104/4824
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Browsing Computer Science Technical Reports by Subject "Digital Simulation"
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Item Event Driven Simulation without Loops or Conditionals(2009-11-05T16:42:01Z) Maurer, Peter M.Event driven simulation normally requires a great deal of computation to perform a multitude of different tasks. The purpose of this paper is to show that none of these computations are necessary. Most computations are devoted to computing new states for other data structures. The technique presented here does not use state variables or any other type of state code. Subroutine addresses are used instead to maintain states. This permits the elimination of all state-testing code, and all state computation code. Our technique is significantly faster than conventional event-driven simulation. Unlike other techniques that focus on state-machine based simulation, our technique can easily be extended to virtually any logic model and any delay model.Item The FHDL LCC Simulator(2009-11-13T15:44:43Z) Maurer, Peter M.This software is the levelized compiled code simulator for the FHDL system. Given a .ckt file, it will compile the file into a C program that simulates the circuit. The C program will be compiled into an executable by the FHDL program. See the FHDL manual in this collection for information about how to use this simulator.Item The FHDL Manual(2009-10-28T15:46:02Z) Maurer, Peter M.The Functional Hardware Design Language can be used to create all parts of a digital design. It can be used to design logic-level circuits with ordinary gates, flip-flops and mid-sized functional blocks. It is hierarchical in nature and can support any type of hierarchical design. It can be used to design ROMs, PLAs, and Algorithmic State Machines. Simulations can be controlled through a high-level-language interface. This interface can be used to design test benches and to perform component-level testing on hierarchical designs. A powerful macro language can be used to create parameterized functional blocks and expression-level circuits. The language is extensible and may provide other features in the future.Item The FHDL Rom Tools(2009-11-13T15:36:00Z) Maurer, Peter M.The FHDL (Functional Hardware Design Language) ROM tools provide a method for specifying, simulating, and automatically laying out ROMs. The primary focus of the ROM tools is on providing powerful methods for specifying microcode. Because the ROM tools were designed to support both VLSI design projects and other course work in hardware design, the ROM language contains many features that allow it to emulate other ROM programming languages. This allows students to complete laboratory exercises using a language that is similar to the one used in their textbook. Once the contents of a ROM have been specified, the ROM can be simulated concurrently with the simulation of the other hardware comprising the design. This allows designs to be debugged before they are fabricated. Once a design has been completely verified, the ROM can be laid out automatically and incorporated into a larger VLSI circuit.Item The Functional Hardware Design Language(2009-10-28T15:45:08Z) Maurer, Peter M.The Functional Hardware Design Language is an expandable language that is designed to make it easy to specify gate-level. FHDL currently supports the specification of gates, high-level functional blocks, state machines, ROM and PLA contents, and parameterized functional blocks. The language is easily extendable.Item The Hyper-Linear Package(2009-11-13T15:51:23Z) Maurer, Peter M.The Hyper-Linear package is the core of the hyper-linear simulation technique described in Reference 1. Given the specification of a Boolean function, the package will detect all partial and total symmetries and return the appropriate multi-dimensional hyper-linear structure. This structure can then be probed for the purpose of generating simulation code. This version of the Hyper-Linear package has the tweaks necessary for detecting conjugate symmetry. Use of conjugate symmetry is the default, but this can be suppressed by using lower-level function calls.Item HyperSim(2009-11-13T15:46:08Z) Maurer, Peter M.This software package implements the simulation algorithm described in the tech report “Using GF(2) matrices in Simulation and Logic Synthesis” found in this archive. (http://hdl.handle.net/2104/5263). This package is part of the FHDL system. Two executable files are produced HyperSim(.exe) and HyperSimA(.exe). HyperSimA is the preferred implementation. This package depends on the connlib and hyper2 packages also available from this archive.Item The Inversion Algorithm for Digital Simulation(2009-11-05T16:45:25Z) Maurer, Peter M.The Inversion Algorithm is an event-driven algorithm, whose performance rivals or exceeds that of Levelized Compiled code simulation, even at activity rates of 50% or more. The Inversion Algorithm has several unique features, the most remarkable of which is the size of the run-time code. The basic Algorithm can be implemented using no more than a page of run-time code, although in practice it is more efficient to provide several different variations of the basic algorithm. The run-time code is independent of the circuit under test, so the algorithm can be implemented either as a compiled code or an interpreted simulator with little variation in performance. Because of the small size of the run-time code, the run-time portions of the Inversion Algorithm can be implemented in assembly language for peak efficiency, and still be retargeted for new platforms with little effort.Item The Inversion-Algorithm Software(2009-11-13T15:41:49Z) Maurer, Peter M.The software in this package implements four versions of the Inversion algorithm. Four executable files are produced.These executables are used in much the same way as the FHDL package, but only AND, OR, NAND, NOR, NOT, BUFF, XOR, and XNOR gates are supported. The four executables are Inversion.exe/Inversion RemoveNots.exe/RemoveNot, CollapseHomo.exe/CollapseHom, and CollapseHetero.exe/CollapseHet. The software will compile under Linux/gcc and under Visual C++. The above list gives the executable names for the two systems. See “The Inversion Algorithm …” in this archive for more information. This software is intended primarily for performance studies.Item The ISCAS85 Benchmarks in FHDL Format(2009-11-13T15:49:29Z) Maurer, Peter M.The three files that constitute this tech report are ISCAS85.fhdl.zip, ISCAS85.InputVectors.zip, and ISCAS85.VectorGenerators.zip. The first file contains the 10 ISCAS85 benchmarks in FHDL format, plus the smoke-test circuit in FHDL format. The second file contains 10 vector files, one for each of the 10 benchmark circuits. Each vector file contains 500,000 input vectors. Each vector is terminated by an end-of-line character, and within each vector, the input values are separated by commas. The final file contains the generators used to generate the random vectors. They are given in two formats, DGL, and C. The C files were generated by the DGL compiler. Once the C files are compiled, they will generate random vectors on stdout. The starting point is the same, but a seed file is written to permit successive calls to produce different outputs. The default number of vectors is 100. Invoke the command with a numeric argument to generate a different number of vectors.Item The ISCAS89 Benchmarks in FHDL Format(2009-11-13T15:47:37Z) Maurer, Peter M.The .zip file contains each of the ISCAS89 Benchmarks in FHDL format. Also included is a random vector generator file for each circuit. (For what it’s worth.) The generators are written in the DGL language.Item The Parallel Technique Software Package(2009-11-13T15:37:46Z) Maurer, Peter M.This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.Item The PC-Set Method Software Package(2009-11-13T15:06:35Z) Maurer, Peter M.This is the software described in the technical report “Two New Techniques for Unit-Delay Compiled Simulation” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.Item The Shadow Algorithm Software Package(2009-11-13T15:39:05Z) Maurer, Peter M.This is the software described in the technical report “The Shadow Algorithm: …” available from this archive. This package is part of the FHDL system and must be installed in your FHDL directory.Item Three-Valued Simulation with the Inversion Algorithm(2009-11-05T16:40:07Z) Maurer, Peter M.The Inversion Algorithm is an event-driven logic simulation technique that is competitive with Levelized Compiled Code Simulation. Previous versions of the Inversion Algorithm have been limited to purely binary simulation. The algorithm presented here extends the Inversion Algorithm to three-valued simulation while preserving the desirable properties of the two-valued algorithm. Because of the richer transformation structure used in three-valued simulation, the scheduling technique is significantly more complex than that of the two-valued algorithm. The procedure for collapsing simultaneous events is also significantly more complex. Once a three-valued net achieves a stable binary value, it is possible to replace the three-valued simulation with a more efficient two-valued simulation. Experimental data shows that the three-valued algorithm is also competitive with levelized compiled code simulation.Item Two New Techniques for Unit-Delay Compiled Simulation(2009-11-05T16:43:41Z) Maurer, Peter M.The PC-set method and the parallel technique are two methods for generating compiled unit-delay simulations of acyclic circuits. The PC-set method analyzes the network, determines the set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on the concept of bit-parallel simulation, is faster and generates less code than the PC-set method, but is not amenable to data-parallel simulation of multiple input vectors. Both techniques are based on the well known levelization algorithm used to generate zero-delay Levelized Compiled Code simulations. Although the parallel technique provides for efficient simulations with a reasonable amount of generated code, there are several opportunities for optimization. The two optimization schemes presented here are called bit-field trimming and shift-elimination. Two different methods of shift elimination are presented, one which is based on breaking cycles in an undirected graph, and one which is based on tracing paths through a network. Performance results are presented for both simulation techniques, and for all optimizations. Comparisons with interpreted event-driven simulation using the ISCAS 85 benchmarks show a factor of 4 improvement for the PC-set method and a factor of ten improvement for the parallel technique. Similar studies for the optimization schemes show an average performance improvement of 47% over the unoptimized simulations.Item Unit Delay Scheduling for the Inversion Algorithm(2009-11-05T16:36:19Z) Maurer, Peter M.The Inversion Algorithm is an event driven algorithm whose performance meets or exceeds that of Levelized Compiled Code simulation, even when the activity rate is unrealistically high. Existing implementations of the Inversion Algorithm are based on the Zero Delay model. This paper presents an implementation which is based on the Unit-Delay model. Although the most basic form of the Inversion Algorithm can be converted to Unit Delay with little difficulty, special considerations must be taken to avoid scheduling conflicts. The main problems discussed in this paper are avoiding scheduling conflicts, and minimizing the amount of storage space required to do so. These problems are made considerably more difficult by the deletion of NOT gates and the collapsing of various connections. These optimizations transform the simulation into a multi-delay simulation under the transport delay model. A complete solution to the scheduling problem is presented under these conditions.Item Using the Connlib Package to Obtain Parsed Netlist Data(2009-11-05T16:48:07Z) Maurer, Peter M.The connlib package can be used to obtain parsed netlist data from “.ckt” files. These files must be created using the Functional Hardware Description Language FHDL. This data can be used in any way you choose. The ISCAS85 and ISCAS89 packages are available as .ckt files, so these benchmarks can be used to test the software you create.